The present invention relates to fine-tuning process controls during integrated circuit chip manufacturing in order to limit systematic wafer-to-wafer and/or lot-to-lot variability.
Silicon-on-insulator (SOI) wafers have been increasingly in demand for manufacturing integrated circuit chips. Such SOI wafers are typically fabricated using a “smart cut” technique. In this technique, a thermal oxide layer is grown on a bulk silicon wafer and a hydrogen implantation process is performed to form a cleavage plane within the bulk silicon wafer. The bulk silicon wafer is then bonded to a handle wafer and split in two at the cleavage plane, thereby forming the SOI wafer. Additional processing includes frontside smoothing (e.g., by polishing or thermal annealing) and backside roughening (e.g., by a coarse wheel grinder) to prevent slippage during automated robot handling.
Oftentimes integrated circuit chip manufacturers use SOI wafers from different suppliers that use slightly different techniques and/or equipment to form the SOI wafers and/or use SOI wafers from a single supplier with different wafer fabrication facilities that use slightly different techniques and/or equipment to form the SOI wafers. Recently, it has been discovered that systematic variations occur on integrated circuit chips manufactured on SOI wafers from different suppliers. For example, average metal wire width and, thereby average metal wire resistance (also referred to as sheet resistance) varies significantly between integrated circuit chips manufactured according to the same integrated circuit chip design on SOI wafers from different suppliers. Such systematic variations can have a negative impact on yield.